1. Field of the Invention
The present invention relates to electronic circuits on semiconductor chips. More specifically, the present invention relates to a capacitively coupled amplifier that facilitates communication between semiconductor chips.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, including tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem is beginning to create a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled via a coupling capacitor with receiver pads on the second chip, it becomes possible to transmit electrical signals directly from the first chip to the second chip without having to route the electrical signal through intervening signal lines within a printed circuit board.
However, capacitively coupled inter-chip communication poses technical challenges. For example, the coupling capacitor blocks the transmission of a DC component in the electrical signals. This limitation requires a receiver amplifier to set a DC voltage of an input to the receiver amplifier. It is difficult to set the DC voltage in order to balance signal and noise considerations. The DC voltage should ideally sensitize the receiver amplifier to transitions in a coupled electrical signal, but should desensitize the receiver amplifier to noise from adjacent channels and circuits. Exacerbating the challenge of setting the DC voltage, the coupling capacitance may vary over two or more orders of magnitude, causing a large variation in signal and noise amplitudes.
FIG. 1 shows an existing circuit 100 for receiving data 106 sent through a coupling capacitor 110. The transmitter circuit is a simple inverter 112 that produces a data signal on a transmitter pad at node Vtx 114 that transitions between ground and Vdd. Note that parasitic capacitor 116, coupled to a grounding mechanism 108 for coupling node Vtrx 114 to electrical ground, does not affect the amplitude of the data signal. Rather, capacitor 116 only slows the transitions in the data signal on node Vtx 114.
The coupling capacitor 110 couples an electrical signal corresponding to the data signal onto a receiver pad at node Vrx 118. The amplitude of the electrical signal on node Vrx 118 is given by the capacitor divider that includes the coupling capacitor 110 divided by the total capacitance on node 118, including a parasitic capacitor 120. A receiver circuit 122 includes a forward path 124 and a reverse path 126 in a feedback loop. The forward path 124 uses a first inverter 128 and a second inverter 130 to amplify the small electrical signal on node Vrx 118 to full digital signal levels. The reverse path 126 uses an inverter 132 that drives voltages Vhi 134 or Vlo 136 back onto node Vrx 118. Voltages Vhi 134 and Vlo 136 are set slightly higher and lower than a switching-threshold voltage, Vth, of the first inverter 128 in the forward path 124 in the receiver circuit 122. For example, Vhi 134 maybe 50 to 150 mV above Vth, and Vlo 136 maybe 50 to 150 mV below Vth.
Resistor Rfb 138 controls a time constant of the feedback loop to be slower than a transition time of the transitions in the data signal on node Vtx 114. The inverter 132 creates a latching action to hold a transition in the electrical signal until the next transition occurs. Therefore, the inverter 132 sets the DC voltage of an input of the receiver circuit 122.
However, the DC voltages may have no relation to the actual amplitude of the data signal on node Vtx 114 and the electrical signal coupled from Vtx 114 through the coupling capacitor 110 to node Vrx 118. For example, DC voltages Vhi 134 and Vlo 136 of 150 mV above and below Vth, respectively, may be suitable when the capacitance of the coupling capacitor 110 is large. When the capacitance of the coupling capacitor 110 is smaller, however, the coupling capacitor 110 may not result in a large enough amplitude of the electrical signal on node Vrx 118 to cross the switching-threshold voltage Vth. Alternatively, DC voltages Vhi 134 and Vlo 136 of 50 mV above and below Vth, respectively, may allow the combination of crosstalk noise and the electrical signal on node Vrx 118 to cross the switching-threshold voltage Vth of the first inverter 128 resulting in an erroneous output 140.
What is needed is an electronic circuit to facilitate capacitive inter-chip communications without the problems listed above.